Efficient pMOS ESD protection circuit

US6963111B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Vijay Reddy · Orlando, US
• Gianluca Boselli · Farmers Branch, US
• Ekanayake A. Amerasekera · Plano, US

Key dates

• Filing date: Jun 13, 2003
• Grant date: Nov 8, 2005
• Expiry date: Jun 13, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/815

Abstract

A pMOS transistor (601) is located in an n-well (602) and has at least one gate (603). Transistor (601) is connected between power pad Vdd or I/O pad (604) and ground potential Vss (605). Gate (603) is connected to power pad (604). The n-well (602) is capacitively (620) coupled to ground (605), decoupled from the transistor source (606) and floating under normal operating conditions. Under an ESD event, the diode formed by the source (606) and the n-well (602) is forward biased (n-well negatively biased) to turn on the lateral pnp transistor to discharge the ESD current. The well voltage keeps increasing up to the value that triggers the lateral bipolar pnp transistor. The ESD protection is scalable with the width of gate (603), improving with shrinking gate width.