Method to include delta-I noise on chip using lossy transmission line representation for the power mesh
US6963204B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2004 |
| Grant date | Nov 8, 2005 |
| Priority date | — |
| Expiry date | Apr 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method for analyzing the noise prediction within one or more electrical circuits, wherein the electrical circuits have a power mesh grid distribution system that feeds power levels to the electrical circuits that are connected by signal wires. After identifying a driver and receiver electrical circuit to be analyzed, a power block is generated that is associated with the driver and receiver electrical circuit by partitioning an area of a power mesh grid distribution system into a power block that can be modeled with lossy transmission line techniques. Next, signal wires situated between the driver and receiver electrical circuits are partitioned into signal blocks that can be modeled with lossy transmission line techniques. Lastly, the power blocks and signal blocks associated with the electrical circuits are analyzed in order to predict the noise performance within the electrical circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.