MAC bus interface
US6963535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2000 |
| Grant date | Nov 8, 2005 |
| Priority date | — |
| Expiry date | Aug 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/324
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A Media Access Control (MAC) Bus interface definition and multiplexor scheme that may be implemented to provide chip layout-insensitive connections between a number of communication physical layer port entities and a single buffer manager or communications controller entity, utilizing a set of independent pipelined buses. The interface comprising three buses: A MAC In Data bus, a MAC Out Data bus, and a MAC Out Message bus. Each bus can operated with an independent set of timing signals to enable data transfers between a system side block and one or more network side blocks. The multiplexor scheme provides a multiplexor for each of the MAC buses, and enables a single system side block to connect to multiple network side blocks. The multiplexors may be also be cascaded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.