Multi-chip wafer level system packages and methods of forming same
US6964881B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2002 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Aug 27, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die are contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with the active surface of the semiconductor dice facing up, wherein metal layer connections are formed and coupled bond pads or other electrical connectors of the semiconductor dice.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.