Method of forming a narrow gate, and product produced thereby
US6964929B1 · kind B1 · utility
2Cited by
19References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 2002 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | May 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor structure includes trimming a patterned hard mask with a wet etch, wherein the hard mask is on a gate layer; and etching the gate layer. In making multiple structures on a semiconductor wafer, an average width of lines in the patterned hard mask is trimmed by at least 100 Å.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.