Sample-and-hold with no-delay reset
US6965258B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2004 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Jul 12, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having a sample-and-hold device is provided, which can be operated in successive cycles which each include a sample phase and a hold phase. During a sample phase a first storage device is charged to a voltage value proportional to an analog input signal, which voltage value is provided for a further circuit part of the integrated circuit in the hold phase. A second storage device is charged during a first cycle to a voltage value which is inverted relative to a final voltage value of the first storage device in the hold phase. In the sample phase of the next cycle following the first cycle, the second storage device is connected to the first storage device in order to discharge the first storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.