Electro-static discharge protection circuit

US6965503B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• John Connor · Burlington, US
• Robert J. Gauthier, Jr. · South Burlington, US
• Christopher S. Putnam · South Burlington, US
• Alan L. Roberts · Jericho, US

Key dates

• Filing date: Sep 30, 2003
• Grant date: Nov 15, 2005
• Expiry date: Sep 30, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/819

Abstract

An ESD protection circuit including the following: one or more inverters (I1, I2, I3), each of the one or more inverters having an input and an output; an RC network (11) having an output node (RCT), output node (RCT) connected with the input of at least one of said one or more inverters; a clamping device (N3) joined with the output of at least one of one or more inverters (I1, I2, I3); and a feedback device (NKP) in communication with clamping device (N3) and output node (RCT) of RC network (11). An RC network may include one or more resistors, and one or more decoupling capacitors. In one embodiment, feedback device (NKP) is an NFET and each of one or more inverters (I1, I2, I3) includes a PFET and NFET pair (P0/N0, P1/N1, P2/N2).