Apparatus and method for controlling data output of a semiconductor memory device
US6965532B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 2003 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Dec 22, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data output control apparatus and method of a semiconductor memory device exactly synchronize the first read data with a clock signal by solving a problem that the first read data is faster than the clock signal as much as a transit time from a voltage level Vddq/2 to a power voltage Vddq or a ground voltage Vssq. For the purpose, the apparatus for sequentially outputting a plurality of read data stored in the semiconductor memory device includes a first path through which a first read data output control signal for controlling the output of the first read data among the plurality of read data is passing, and a second path through which a second data output control signal for controlling the output of the other read data following the first read data among the plurality of read data is passing, wherein the first read data output control signal is delayed as much as the transit time and outputted through the first path in response to a preamble time control signal for reporting the start of a data read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.