Size checking method and apparatus
US6965687B2 · kind B2 · utility
5Cited by
3References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2001 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Apr 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pair of edges that are located at ends as viewed in the widthwise direction of a design pattern are recognized. On the basis of the edge direction in which the paired edges are recognized, edge points on the design pattern are detected as sub-pixels. The widthwise dimension of the design pattern is calculated on the basis of the edge points. In addition, the widthwise dimension of a circuit pattern is calculated at the same position as the widthwise dimension of the design pattern. On the basis of the calculated widthwise dimensions, the semiconductor wafer circuit pattern is checked.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.