Memory column redundancy circuitry and method for implementing the same
US6966012B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 2002 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Nov 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A column redundancy circuitry and a method for implementing the same are provided. One exemplary method provides routing for an access request addressed to a defective cell. The method includes providing a redundant column within a memory circuit, the redundant column in communication with a sense amplifier. Next, a defective cell of a memory circuit is located and the address is programmed. An access request is then processed, the access request containing the address of the defective cell Finally, the access request is routed to the redundant column through enable circuitry. Some notable advantages include the conservation of surface area of the memory circuit induced by locating the redundant column within the memory circuit. The externalization of the fuse box, Built In Self Repair region and the logic circuitry from the memory core also provide increased flexibility.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.