Method for synchronizing and resetting clock signals supplied to multiple programmable analog blocks
US6967511B1 · kind B1 · utility
62Cited by
7References
25Claims
0Family size
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Key dates
| Filing date | Oct 1, 2001 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | May 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/151
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for establishing frequency and phase alignment of clock signals across a domain of analog blocks coupled in a single integrated circuit. Different analog functions are implemented by selectively and electrically coupling different combinations of analog blocks. The analog blocks may be arrayed in a number of columns. A synchronized clock signal is supplied to all of the analog blocks in a combination of blocks, even when the blocks are in different columns. The frequency of the clock signal can be changed dynamically depending on the analog function to be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.