Method and apparatus for improving cycle time in a quad data rate SRAM device
US6967861B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2004 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | May 21, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for implementing a self-timed, read to write operation in a memory storage device. In an exemplary embodiment, the method includes capturing a read address during a first half of a current clock cycle, and commencing a read operation so as to read data corresponding to the captured read address onto a pair of bit lines. A write operation is commenced for the current clock cycle so as to cause write data to appear on the pair of bit lines as soon as the read data from the captured read address is amplified by a sense amplifier, wherein the write operation uses a previous write address captured during a preceding clock cycle. A current write address is captured during a second half of the current clock cycle, said current write address used for a write operation implemented during a subsequent clock cycle, wherein the write operation for the current clock cycle is timed independent of the current write address captured during said second half of the current clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.