Combination NAND-NOR memory device
US6967870B2 · kind B2 · utility
6Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2004 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Jan 7, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit memory device has an array of non-floating gate non-volatile flash cells arranged in a NOR configuration. The device further has page buffers and control circuits to operate the array in either a NAND mode of operation or a NOR mode of operation. Finally, the array is partitionable by a user into two partitions such that one partition operates only in the NAND mode while the other partition operates only in a NOR mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.