Redundancy architecture for repairing semiconductor memories
US6967878B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 24, 2003 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Oct 28, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/785
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy architecture for improving the throughput of testing and repairing the semiconductor memory after packaging. A memory device is composed of a memory cell array including memory cells and first redundant cells, a data comparator comparing read data received from the memory cell array with anticipated data provided by an external tester to produce a data mismatch signal, a redundancy mapping circuit responsive to the data mismatch signal for detecting a defective address of the memory cell array, a nonvolatile memory storing the detected defective address, and a redundancy circuitry repairing the memory cell array by replacing ones of the memory cells associated with the defective address with the first redundant cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.