Address scramble
US6967896B2 · kind B2 · utility
27Cited by
148References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2003 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Apr 25, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a memory cell array, the method comprising assigning word lines of a memory cell array as addresses for writing sets of data thereto from a cache memory, and scrambling addresses of the sets of data by writing a first chunk of the particular set of data from the cache memory to a first word line of the array, and writing a second chunk of the particular set of data from the cache memory to a second word line of the array, the first chunk comprising a first subset of the particular set of data and the second chunk comprising a second subset of the particular set of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.