Built-in self test circuit for testing cache tag array and compare logic
US6968427B1 · kind B1 · utility
6Cited by
14References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2002 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Oct 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory comprising: 1) a tag array comprising a plurality of tag entry locations that are accessed by R of the M least significant bits of an N-bit received address and stored an address tag comprising the (N-M) most significant bits of the N-bit received address. The cache memory also comprises 2) cache hit comparison circuitry for comparing the (N-M) most significant bits of an N-bit received address with an address tag and generating a HIT signal if a match occurs, and 3) tag array test circuitry for testing the operation of the tag array and the cache hit comparison circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.