Layout design and process to form nanotube cell for nanotube memory applications
US6969651B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2004 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Mar 26, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/943
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Nanotube memory cells are formed on a semiconductor substrate. Lower and upper memory cell chambers are formed by forming a first trench overlying the first and second contacts in a nitride layer, forming a second trench overlying the first and second contacts in a dielectric layer, depositing a nitride layer on the combined lower and upper chambers, and patterning the nitride layer to form an access hole to the nanotube layer and a second access hole to the second contact. A conductive layer is then deposited and patterned to form a top electrode contact and a nanotube layer contact. The conductive material closes the aperture created by the access hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.