Method of making a planarized semiconductor structure
US6969684B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2001 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Sep 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31055
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for eliminating a polish stop layer from a polishing process. In particular, a method is provided which may include polishing an upper layer of a semiconductor topography to form an upper surface at an elevation above an underlying layer, wherein the upper surface does not include a polish stop material. Preferably, the upper surface of the topography formed by polishing is spaced sufficiently above the underlying layer to avoid polishing the underlying layer. The entirety of the upper surface may be simultaneously etched to expose the underlying layer. In an embodiment, the underlying layer may comprise a lateral variation in polish characteristics. The method may include using fixed abrasive polishing of a dielectric layer for reducing a required thickness of an additional layer underlying the dielectric layer. Such a method may be useful when exposing an underlying layer is desirable by techniques other than polishing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.