Etching a dielectric layer in an integrated circuit structure having a metal hard mask layer
US6969685B1 · kind B1 · utility
7Cited by
4References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2002 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Sep 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32136
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to the etching of a dielectric layer in an integrated circuit (IC) structure having a patterned metal hard mask layer. The method comprises feeding a gas mixture that includes a carbon monoxide (CO) and at least one fluorocarbon gas mixture into a reactor. The gas mixture has no oxygen (O2) gas. The gas mixture is then converted into a plasma. The plasma selectively etches the dielectric layer. Typically, the dielectric layer comprises silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.