Memory device having isolation trenches with different depths and the method for making the same
US6969686B2 · kind B2 · utility
12Cited by
5References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 28, 2003 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Oct 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a memory device utilizes multi-etching processes to respectively construct isolation trenches in a memory substrate that has a memory array area and a peripheral circuit region, wherein the depth of the trenches in the peripheral circuit region is deeper into the memory substrate than the depth of the trenches in the memory array area. Therefore, possible current leakage caused from the high operating voltage is effectively mitigated, and the performance of the memory device is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.