Surround-gate semiconductor device encapsulated in an insulating medium
US6969878B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2003 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Apr 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6744
Abstract
A semiconductor device is provided that includes a semiconductor channel region extending above a semiconductor substrate in a longitudinal direction between a semiconductor source region and a semiconductor drain region, and a gate region extending in the transverse direction, coating the channel region, and insulated from the channel region. The source, channel, and drain regions are formed in a continuous semiconductor layer that is approximately plane and parallel to the upper surface of the substrate. Additionally, the source, drain, and gate regions are coated in an insulating coating so as to provide electrical insulation between the gate region and the source and drain regions, and between the substrate and the source, drain, gate, and channel regions. Also provided is an integrated circuit that includes such a semiconductor device, and a method for manufacturing such a semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.