Dual gated finfet gain cell

US6970372B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Toshiharu Furukawa · South Burlington, US
• Mark C. Hakey · Saint Albans, US
• David V. Horak · South Burlington, US
• Charles W. Koburger, III · Delmar, US
• Mark E. Masters · South Burlington, US
• Peter H. Mitchell · Jericho, US

Key dates

• Filing date: Jun 29, 2004
• Grant date: Nov 29, 2005
• Expiry date: Jun 29, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.