Memory device and method of reading data from a memory device
US6970395B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2003 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Sep 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a delay-locked loop circuit having delay elements and a synchronization circuit coupled to the delay-locked loop circuit. The synchronization circuit receives a synchronization enable signal and outputs a plurality of enable signals, including an enable signal coupled to an output circuit. Because the enable signal is synchronized with the read signal, it is possible to provide more time to read data into the buffer. A method of reading data from a memory device couples a synchronization enable signal and an external clock signal to a synchronization circuit. A read signal and an output enable are generated based upon a synchronization enable signal and a delayed clock signal of the external clock signal. Because the output signal is synchronized to the read signal, more time is allowed for the sense function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.