System and method for providing a pre-fetch memory controller
US6970978B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 3, 2002 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Mar 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method is disclosed for providing a pre-fetch memory controller in a computer system that comprises a plurality of master agents. The memory controller comprises a bus interface, a memory interface and a plurality of pre-fetch queues. In one embodiment each pre-fetch queue is assigned to a master agent. In an alternate embodiment the pre-fetch queues are dynamically assigned to master agents. The bus interface services memory read requests, memory write requests, and pre-fetch requests. Data may be pre-fetched from main memory and stored in the pre-fetch queues. This reduces the latency for memory read requests and improves the efficiency of the memory interface with the main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.