Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions

US6970982B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Erik R. Altman · Danbury, US
• Peter G. Capek · Ossining, US
• Michael K. Gschwind · Chappaqua, US
• Harm Peter Hofstee · Austin, US
• James Allan Kahle · Austin, US
• Ravi Nair · Briarcliff Manor, US
• Sumedh W. Sathaye · Austin, US
• John-David Wellman · Hopewell Junction, US

Key dates

• Filing date: Oct 1, 2003
• Grant date: Nov 29, 2005
• Expiry date: Apr 9, 2024

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/682
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.