Power/performance optimized memory controller considering processor power states
US6971034B2 · kind B2 · utility
38Cited by
16References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 9, 2003 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Apr 24, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When a processor in a computer system is placed in a low power mode, power consumption of the computer system may be further reduced by reducing power consumption of one or more components of a memory coupled to the processor and by reducing power consumption of one or more components of a controller device coupled to the memory. The processor and the controller device may share the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.