Aditya Navale
77Patents
8h-index
81Co-inventors
81Inventor score
Filing activity: Sep 28, 2001 → Jan 10, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7149909B2 | Power management for an integrated graphics device | Emerging Cross-Sectional Technologies | 51 | Expired |
| US6971034B2 | Power/performance optimized memory controller considering processor power states | Emerging Cross-Sectional Technologies | 38 | Expired |
| US7222253B2 | Dynamic power control for reducing voltage level of graphics controller component of memory controller based on its degree of idleness | Emerging Cross-Sectional Technologies | 20 | Expired |
| US9323684B2 | Dynamic cache and memory allocation for memory subsystems | Emerging Cross-Sectional Technologies | 18 | Active |
| US7868897B2 | Apparatus and method for memory address re-mapping of graphics data | Physics | 12 | Active |
| US7343502B2 | Method and apparatus for dynamic DLL powerdown and memory self-refresh | Physics | 11 | Expired |
| US8477145B2 | Memory address re-mapping of graphics data | Physics | 10 | Active |
| US9996386B2 | Mid-thread pre-emption with software assisted context switch | Physics | 10 | Active |
| US10282808B2 | Hierarchical lossless compression and null data support | Physics | 8 | Active |
| US7581129B2 | Dynamic power control for reduced voltage level of graphics controller component of memory controller based on its degree of idleness | Emerging Cross-Sectional Technologies | 8 | Active |
| US6871119B2 | Filter based throttling | Physics | 7 | Expired |
| US9626735B2 | Page management approach to fully utilize hardware caches for tiled rendering | Physics | 6 | Active |
| US8037334B2 | Dynamic power control for reduced voltage level of graphics controller component of memory controller based on its degree of idleness | Emerging Cross-Sectional Technologies | 6 | Active |
| US9589159B2 | Creating secure communication channels between processing elements | Electricity | 5 | Active |
| US9396032B2 | Priority based context preemption | Physics | 5 | Active |
| US8301927B2 | Dynamic control of reduced voltage state of graphics controller component of memory controller | Emerging Cross-Sectional Technologies | 4 | Active |
| US9916257B2 | Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory | Physics | 4 | Active |
| US6842807B2 | Method and apparatus for deprioritizing a high priority client | Physics | 4 | Expired |
| US9075741B2 | Dynamic error handling using parity and redundant rows | Electricity | 3 | Active |
| US6898679B2 | Method and apparatus for reordering memory requests for page coherency | Physics | 3 | Expired |
| US10861126B1 | Asynchronous execution mechanism | Emerging Cross-Sectional Technologies | 3 | Active |
| US8510585B2 | Dynamic control of reduced voltage state of graphics controller component of memory controller | Emerging Cross-Sectional Technologies | 3 | Active |
| US9436972B2 | System coherency in a distributed graphics processor hierarchy | Physics | 3 | Active |
| US9304813B2 | CPU independent graphics scheduler for performing scheduling operations for graphics hardware | Emerging Cross-Sectional Technologies | 3 | Active |
| US7353349B2 | Method and apparatus for reordering memory requests for page coherency | Physics | 3 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.