Method for selectively controlling damascene CD bias
US6972258B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2003 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Nov 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for selectively etching a semiconductor feature opening to controllably achieve a critical dimension accuracy including providing a semiconductor wafer including a first opening formed extending through a thickness of at least one dielectric insulating layer and having an uppermost inorganic BARC layer; depositing a photoresist layer over the uppermost BARC layer and patterning the photoresist layer to form an etching pattern for etching a second opening overlying and encompassing the first opening; carrying out a first plasma assisted etching process to etch through a thickness of the BARC layer including a predetermined amount of CO in a plasma etching chemistry to increase an etching resistance of the photoresist layer; and, carrying out a second plasma assisted etching process to etch through a thickness portion of the at least one dielectric insulating layer to form the second opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.