Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
US6972481B2 · kind B2 · utility
83Cited by
32References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 2, 2003 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Aug 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor multi-package module having stacked first and second packages, each package including a die attached to a substrate, in which the first and second substrates are interconnected by wire bonding, and wherein at least one said package comprises a stacked die package. Also, a method for making a semiconductor multi-package module, by providing a stacked die molded first package including a first package substrate, affixing a second molded package including a second substrate onto an upper surface of the first package, and forming z-interconnects between the first and second substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.