Self-timed scan circuit for ASIC fault testing
US6972592B2 · kind B2 · utility
9Cited by
8References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 24, 2003 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Mar 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318558
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A self-timed scan circuit includes a multiplexer for selecting either a data input or a test input in response to an internal test enable signal and for generating a multiplexed output; a latch coupled to the multiplexer for generating a latched output in response to a next clock pulse; and a timing control circuit for generating the internal test enable signal in response to a global test enable signal wherein the internal test enable signal is set to logic one when the global test enable signal is set to logic one and wherein the internal test enable signal is set to logic zero in response to the next clock pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.