Main row decoder in a semiconductor memory device
US6973007B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2004 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Jun 28, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure is a main row decoder of a semiconductor memory device including: a bank controller for generating an internal RAS signal in response to an active and precharge signal; a first pulse generator for generating a first pulse signal when the internal RAS signal transitions; a second pulse generator for generating a second pulse signal when the internal RAS signal or a self refresh signal transitions; an address latch circuit for latching the least significant bit of a row address in response to the first pulse signal; and a row pre-decoder for decoding outputs of the address latch circuit in response to the second pulse signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.