Tracking the most frequently erased blocks in non-volatile memory systems
US6973531B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2002 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Jun 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for performing wear leveling in a non-volatile memory system are disclosed. According to one aspect of the present invention, a method for processing elements included in a non-volatile memory of a memory system includes obtaining erase counts associated with a plurality of erased elements. Each element included in the plurality of elements has an associated erase count that indicates a number of times the element has been erased. The method also includes grouping a number of erased elements included in the plurality of elements into a first set, and storing the erase counts associated with the first set in a memory component of the memory system. Grouping the number of elements into the first set typically includes selecting erased elements included in the plurality of elements which have the highest associated erase counts of the erase counts associated with the plurality of elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.