Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure
US6973613B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2002 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Jan 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/42
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller comprises a check bit encoder circuit and a check/correct circuit. The check bit encoder circuit is coupled to receive a data block to be written to a memory comprising a plurality of memory devices, and is configured to encode the data block with a plurality of check bits to generate an encoded data block. The plurality of check bits are defined to provide at least: (i) detection and correction of a failure of one of the plurality of memory devices; and (ii) detection and correction of a single bit error in the encoded data block following detection of the failure of one of the plurality of memory devices. The check/correct circuit is coupled to receive the encoded data block from the memory and is configured to decode the encoded data block and perform at least the detection of (i) and (ii) on the encoded data block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.