Methods of fabricating integrated circuit devices having uniform silicide junctions
US6974752B2 · kind B2 · utility
3Cited by
1References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2003 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Apr 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/015
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate having sidewalls is formed on an integrated circuit substrate. A barrier layer spacer is formed on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is formed on the portion of the barrier layer spacer protruding from the sidewalls of the gate. Related devices are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.