Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch
US6976095B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1999 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Dec 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from ports in segments and each segment is assigned to one of the program threads. Ordering of segments within packets, and between packets from the same port, is maintained by a scheduler program thread. The scheduler program thread blocks a new assignment of the previously assigned port to a program thread until the program thread to which the port was previously assigned has indicated that it has completed the processing of the segment from that port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.