Method and apparatus for reducing interrupt latency by dynamic buffer sizing
US6976110B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2003 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Jun 1, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing interrupt latency in a data processing system wherein a storage device is provided having a predetermined maximum number of storage locations. Data execution circuitry is coupled to the storage device for providing data to the storage device and storing the data in the storage device. Interrupt control circuitry is coupled to the data execution circuitry, wherein the interrupt control circuitry interrupts the data execution circuitry. The data stored in the storage device is completely outputted, thereby having an associated interrupt latency resulting from the output of the stored data. The storage capacity of the storage device is changed dynamically to minimize the interrupt latency. The storage device has a utilization value that varies between a predetermined minimum number of storage locations and the predetermined maximum number of storage locations based upon an operating mode of the data processing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.