Method and system for controlling default values of flip-flops in PGA/ASIC-based designs
US6976160B1 · kind B1 · utility
39Cited by
86References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 22, 2002 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Dec 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
During a reset condition or prior to system initialization of an FPGA-based system (100), a FPGA (102) can be pre-configured by loading a value from a memory cell (108) into at least one flip-flop (312) of the FPGA, which represents a configuration register for an FPGA memory controller (106). The FPGA memory controller can be configured using the value loaded in the flip-flop. The value loaded into the flip-flop from the memory cell can be a default value previously stored in the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.