Memory/Transmission medium failure handling controller and method
US6976194B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2002 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Jan 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/42
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller may include a check bit encoder circuit and a check/correct circuit. The check bit encoder circuit is coupled to receive a data block to be written to memory, where the memory includes a plurality of memory devices arranged on a plurality of memory modules. Each of the plurality of memory modules includes a plurality of the plurality of memory devices. The check bit encoder circuit is configured to encode the data block with a plurality of check bits to generate an encoded data block. The plurality of check bits are defined to provide at least detection of a failure of one of the plurality of memory modules. The check/correct circuit is coupled to receive the encoded data block from the memory, and is configured to detect the failure of one of the plurality of memory modules responsive to decoding the encoded data block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.