Signal via impedance verification tool
US6976233B1 · kind B1 · utility
11Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2003 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Mar 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/23
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method is disclosed for verifying signal via impedance. Properties of a signal via and of any other vias within a given distance of the signal via are read from a circuit design database. A target characteristic impedance value for the signal via is obtained. A characteristic impedance of the signal via is calculated based on the other vias. The signal via is flagged as having an incorrect characteristic impedance if the calculated characteristic impedance does not match the target characteristic impedance value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.