Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit
US6977862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2004 |
| Grant date | Dec 20, 2005 |
| Priority date | — |
| Expiry date | Aug 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit are provided. One embodiment provides a method for addressing memory areas in a memory circuit with successive addresses, with either a regular memory area or a redundant memory area being addressed depending on the address, with an inactive state of a deactivation signal being set when addressing the regular memory area, which inactive state allows the addressing of the regular memory area, with the addressing of the regular memory area being blocked on the basis of an active state of the deactivation signal when addressing the redundant memory area, wherein a change is made from the active state of the deactivation signal to the inactive state of the deactivation signal before the application of the next address for addressing one of the memory areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.