Method and apparatus for performing cache segment flush and cache segment invalidation operations
US6978357B1 · kind B1 · utility
17Cited by
8References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 24, 1998 |
| Grant date | Dec 20, 2005 |
| Priority date | — |
| Expiry date | Jul 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for including in a computer system, instructions for performing cache memory invalidate and cache memory flush operations. In one embodiment, the computer system comprises a cache memory having a plurality of cache lines each of which stores data, and a storage area to store a data operand. An execution unit is coupled to the storage area, and operates on data elements in the data operand to invalidate data in a predetermined portion of the plurality of cache lines in response to receiving a single instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.