Memory test system for peak power reduction
US6978411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2002 |
| Grant date | Dec 20, 2005 |
| Priority date | — |
| Expiry date | Dec 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory test system for peak power reduction. The memory test system includes a plurality of memories, a plurality of memory built-in self-test circuits and a plurality of delay units. Each of the memory built-in self-test circuits comprises a built-in self-test controller for receiving a clock signal and producing a plurality of required control signals to test one of the memories. Each of the delay units is coupled between two adjacent built-in self-test controllers. The clock signal input to one of the built-in self-test controllers is received by the delay unit to produce a delayed clock signal, and the delay unit outputs the delayed clock signal to the other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.