Method and apparatus for manufacturing semiconductor device
US6979577B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 10, 2003 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Jan 21, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70633
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Concerning a plurality of wafers which compose one lot, amounts of misalignment between alignment marks of these wafers and alignment patterns transferred on photoresists are measured in advance, and then, a mutual relation between a thickness of an interlayer dielectric film and a value of Wafer Scaling is calculated. When exposure is actually executed, first, an interlayer dielectric film is formed on the alignment marks in a lot and planarized. After that, the thickness of the interlayer dielectric film after planarization is measured. The value of the Wafer Scaling is estimated from an average value of the thicknesses of the interlayer dielectric films in the lot and the above-mentioned mutual relation. Then, photoresists are coated on the interlayer dielectric films in the lot, and the photoresists are exposed while the correction is executed so as to compensate the value of the Wafer Scaling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.