Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks
US6979609B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2003 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Jul 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
Abstract
A method for processing dual threshold nMOSFETs and pMOSFETs requiring only one additional masking and implantation operation over single threshold MOSFETs is disclosed. The additional mask and implant operation both enhances the threshold voltage doping of one type of FET and compensates the threshold voltage doping of another type of FET. Where a first threshold voltage implant sets the threshold voltage for an NMOS device to a low threshold voltage, and a second threshold voltage implant sets the threshold voltage for a PMOS device to a high threshold voltage, a third implant may both enhance a NMOS device threshold implant to set the threshold voltage high while compensating a PMOS device threshold implant to set the threshold voltage low.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.