System and method for forming a semiconductor with an analog capacitor using fewer structure steps

US6979615B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Imran Khan · Richardson, US
• Louis N. Hutter · Richardson, US
• James Todd · Plano, US
• Jozef Mitros · Richardson, US
• William Nehrer · Soquel, US

Key dates

• Filing date: Sep 12, 2002
• Grant date: Dec 27, 2005
• Expiry date: Sep 12, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.