Method for fabricating a flash memory cell
US6979620B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2005 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | May 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method for fabricating a flash memory cell is provided. After an ONO dielectric layer is formed on a first conductive layer over a tunnel oxide layer, a second conductive layer is formed on the ONO dielectric layer. Then, patterning the second conductive layer to form a periphery region comprising an exposed portion of a semiconductor substrate and a memory cell region comprising the left second conductive layer. During the present process, the ONO dielectric layer is protected from being exposed in various solvents and gases with the second conductive layer. Thus, a flash memory cell with a high-quality ONO gate dielectric layer, without increasing complexity of the process and additional masks, is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.