Method for fabricating split gate transistor device having high-k dielectrics
US6979623B2 · kind B2 · utility
41Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2003 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Dec 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and systems are disclosed that facilitate semiconductor fabrication by fabricating transistor devices having gate dielectrics with selectable thicknesses in different regions of semiconductor devices. The thicknesses correspond to operating voltages of the corresponding transistor devices. Furthermore, the present invention also provides systems and methods that can fabricate the gate dielectrics with high-k dielectric material, which allows a thicker gate dielectric than conventional silicon dioxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.