Isolation trench

US6979627B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Choh Fei Yeap · San Diego, US
• Yongjoo Jeon · Austin, US
• Michael D. Turner · Plymouth, US
• Toni D. Van Gompel · Austin, US

Key dates

• Filing date: Apr 30, 2004
• Grant date: Dec 27, 2005
• Expiry date: Apr 30, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/01
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process for forming an isolation trench in a wafer. The process includes depositing (e.g. by a directional deposition process) a first dielectric material in the trench and then depositing a second dielectric material (e.g. by a directional deposition process) over the first dielectric material in the trench. A third material is deposited in the trench on the second layer. The second material and the third material are selectively etchable with respect to each other. In one example, the first material has a lower dielectric constant than the second material.