Optimization of die yield in a silicon wafer “sweet spot”
US6980917B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Feb 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70433
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of increasing the wafer yield for an integrated circuit includes the steps of receiving as input a shot map, an initial orientation of a center of the shot map relative to a center of a wafer resulting in a maximum number of printable die, a usable wafer diameter, a selected yield margin, and historical yield information for each die location in the shot map; generating a plot of an estimated yield for each die location in the wafer from the historical yield information; plotting an estimated wafer yield within an area of the wafer as a function of a radius; and selecting a sweet spot radius corresponding to an area of the wafer having a wafer yield that is substantially equal to the selected yield margin for finding an offset from the initial orientation of the center of the shot map that results in a maximum wafer yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.