Mapping and logic for combining L1 and L2 directories and/or arrays
US6981096B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1998 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Oct 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Architectures, methods and systems are presented which combine a multiple of directories (e. g. L1 and L2 directory) into a single directory, while still allowing the individual levels to use their own organization which is best for overall performance. This integration is performed without compromising the organization at each level. With some small additions to the L2 directory, it is used simultaneously to perform both the L1 and L2 directory functions. Additionally, the same organizational structure allows the L2 array to serve both as a traditional L1 and simultaneous L2 array. In one aspect of the present invention an architecture is provided for a first and second level memory hierarchy, or cache, including a first data storage array for the first level memory hierarchy; a second data storage array for the second level memory hierarchy, a single address translation directory combining the directories for the first and second level memory hierarchy into a single directory satisfying the organization requirements of both the first and second level memory hierarchy. Also provided is a system having three level memory hierarchy comprising: a single combined directory used to ser…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.